Mining scheme of FPGA
Publish: 2021-03-22 06:36:11
1. FPGA is free, it seems that mining costs a lot of electricity, Taobao seems to sell information program before
2.
Mining chip has gone from CPU mining to GPU mining to FPGA mining, and now it has entered the era of ASIC mining. However, the way of mining has also experienced from one or two mining machines to small mining machine workshops, and now it has entered the era of large-scale mining
(1) mining mode: from one miner to large-scale mine
if you start to try mining, you need to prepare a miner, a computer with internet connection, an AUC, a raspberry pie, power supply and various connecting cables. The connection order of various devices is network cable - & gt; Raspberry pie - & gt; Microusb cable - & gt; AUC-> 4Pin cable - & gt; Mining machine and power supply
3. The purpose of mining is to package the transaction block. If the package is successful, you will open a new package and get a 25 bitcoin reward, as well as the handling charge for the future transactions added to the package
then other miners will start to package the transaction generated by your new package until the next package comes out first
in the future, the mining capacity of bitcoin will be small or even zero. You still have transaction fees. The system will always need miners, and mining machines will still exist.
then other miners will start to package the transaction generated by your new package until the next package comes out first
in the future, the mining capacity of bitcoin will be small or even zero. You still have transaction fees. The system will always need miners, and mining machines will still exist.
4. In fact, FPGA based high-speed signal acquisition is almost the same design principle. First, ADC samples the signal, converts the analog signal into digital signal, and then sends it to FPGA. At this time, FPGA needs to write three IP moles:
IP core 1, state machine to control ADC automatic high-speed conversion. Its function is to achieve high-speed 100m signal sampling, which is a cycle of timing control. After the ADC conversion is completed once, the FPGA reads the data and hands it to the second IP core (FIFO cache control IP), and then reads the second data immediately. But we need to pay attention to the selection of ADC chip, the conversion rate of ADC must be higher than 100MHz
IP core 2, FIFO cache control core: if you want to achieve high reliability and stability of data acquisition, FIFO generally must exist. The IP core of FIFO determines whether the ADC one-time sampling ends. If it ends, the data will be stored in FIFO buffer 1. Then, in the second sampling, the IP core 3 reads the data from the cache 1, empties the data from the cache 1, and stores the second read sampling data into the cache 2. Then, the IP core 3 reads the second read data from the cache 2, and the ADC samples the coexisting data into the cache 1 In other words, FIFO is divided into two buffers, one is always used to store the data after ADC conversion, and the other is used to let the later function moles read the last sampled data. The two are simultaneous. Buffer 1 and buffer 2 work alternately.)
IP core 3: a functional mole for processing digital signals. You said that your task is ADC conversion, so IP core 3 you only need to read the data of two FIFO buffers alternately<
answer your supplementary question:
1. Does low speed not need FIFO mole
A: FIFO can be omitted at both high speed and low speed, just for the stability of the system, the stability of the sampling rate, and the high reliability of the collected data, so the second FIFO buffer is added
2. What should be paid attention to in high speed signal PCB wiring
A:
1. Power filter must be done well, otherwise there will be ripple
2. It is better to use two GND to clamp all the circuits of the positive power supply (VCC) (if the whole board is covered with copper, this can be ignored)
3. The two sides of the double panel need to be perpendicular to each other, which can rece EMC
4. Analog power and digital power are separated, so is ground. The digital power supply and analog power supply on the whole board are connected by two 0 ohm resistors 1 power supply positive, 1 ground)
5. It is better to lay copper.
IP core 1, state machine to control ADC automatic high-speed conversion. Its function is to achieve high-speed 100m signal sampling, which is a cycle of timing control. After the ADC conversion is completed once, the FPGA reads the data and hands it to the second IP core (FIFO cache control IP), and then reads the second data immediately. But we need to pay attention to the selection of ADC chip, the conversion rate of ADC must be higher than 100MHz
IP core 2, FIFO cache control core: if you want to achieve high reliability and stability of data acquisition, FIFO generally must exist. The IP core of FIFO determines whether the ADC one-time sampling ends. If it ends, the data will be stored in FIFO buffer 1. Then, in the second sampling, the IP core 3 reads the data from the cache 1, empties the data from the cache 1, and stores the second read sampling data into the cache 2. Then, the IP core 3 reads the second read data from the cache 2, and the ADC samples the coexisting data into the cache 1 In other words, FIFO is divided into two buffers, one is always used to store the data after ADC conversion, and the other is used to let the later function moles read the last sampled data. The two are simultaneous. Buffer 1 and buffer 2 work alternately.)
IP core 3: a functional mole for processing digital signals. You said that your task is ADC conversion, so IP core 3 you only need to read the data of two FIFO buffers alternately<
answer your supplementary question:
1. Does low speed not need FIFO mole
A: FIFO can be omitted at both high speed and low speed, just for the stability of the system, the stability of the sampling rate, and the high reliability of the collected data, so the second FIFO buffer is added
2. What should be paid attention to in high speed signal PCB wiring
A:
1. Power filter must be done well, otherwise there will be ripple
2. It is better to use two GND to clamp all the circuits of the positive power supply (VCC) (if the whole board is covered with copper, this can be ignored)
3. The two sides of the double panel need to be perpendicular to each other, which can rece EMC
4. Analog power and digital power are separated, so is ground. The digital power supply and analog power supply on the whole board are connected by two 0 ohm resistors 1 power supply positive, 1 ground)
5. It is better to lay copper.
5. Just download a gpu360 miner
common computer mining methods:
1. Download and install gpu360 miner
2. The software will be set to boot, it is recommended to boot. Because it has a very human function, when you don't use the computer, it will automatically mine, when you use it, it will stop instantly, it will not affect the normal work and use
3. After the software is started, change it to your own mobile phone number. After the software starts, there are three setting options:
4. The first time you start mining, you will test the equipment, and it will test your best mining scheme. It usually takes about ten minutes
5. After testing, it will automatically enter the mining state
6. Click stop and close to minimize to the tray, so that when you don't use the computer, it will automatically open to make money
right click the icon to shut down the software completely
7. Bitcoin earned can be exchanged directly in online stores.
common computer mining methods:
1. Download and install gpu360 miner
2. The software will be set to boot, it is recommended to boot. Because it has a very human function, when you don't use the computer, it will automatically mine, when you use it, it will stop instantly, it will not affect the normal work and use
3. After the software is started, change it to your own mobile phone number. After the software starts, there are three setting options:
4. The first time you start mining, you will test the equipment, and it will test your best mining scheme. It usually takes about ten minutes
5. After testing, it will automatically enter the mining state
6. Click stop and close to minimize to the tray, so that when you don't use the computer, it will automatically open to make money
right click the icon to shut down the software completely
7. Bitcoin earned can be exchanged directly in online stores.
6. FPGA (field programmable gate array) is the proct of further development based on pal, gal, CPLD and other programmable devices
generally speaking, FPGA is a kind of programmable hardware chip
the circuit design completed by hardware description language (Verilog or VHDL) can be quickly burned to FPGA for testing after simple synthesis and layout, which is the mainstream technology of modern IC design verification. These elements can be used to implement some basic logic gates (such as and, or, XOR, not) or more complex combination functions, such as decoder or mathematical equation. In most FPGAs, these programmable components also contain memory components, such as flip flops or other more complete memory blocks
the system designer can connect the logic blocks in FPGA through an edited connection as needed, just like a circuit test board is placed in a chip. The logic block and connection of a finished FPGA can be changed according to the designer, so the FPGA can complete the required logic functions
basic features:
1) using FPGA to design ASIC (application specific integrated circuit), users don't need to put the chip into proction, they can get a common chip
2) FPGA can be used as the medium chip of other full custom or semi custom ASIC circuits< There are many flip flops and I / O pins in FPGA< 4) FPGA is one of the devices with the shortest design cycle, the lowest development cost and the lowest risk
5) FPGA adopts high-speed CMOS technology with low power consumption and can be compatible with CMOS and TTL levels< It can be said that FPGA chip is one of the best choices for small batch system to improve system integration and reliability.
generally speaking, FPGA is a kind of programmable hardware chip
the circuit design completed by hardware description language (Verilog or VHDL) can be quickly burned to FPGA for testing after simple synthesis and layout, which is the mainstream technology of modern IC design verification. These elements can be used to implement some basic logic gates (such as and, or, XOR, not) or more complex combination functions, such as decoder or mathematical equation. In most FPGAs, these programmable components also contain memory components, such as flip flops or other more complete memory blocks
the system designer can connect the logic blocks in FPGA through an edited connection as needed, just like a circuit test board is placed in a chip. The logic block and connection of a finished FPGA can be changed according to the designer, so the FPGA can complete the required logic functions
basic features:
1) using FPGA to design ASIC (application specific integrated circuit), users don't need to put the chip into proction, they can get a common chip
2) FPGA can be used as the medium chip of other full custom or semi custom ASIC circuits< There are many flip flops and I / O pins in FPGA< 4) FPGA is one of the devices with the shortest design cycle, the lowest development cost and the lowest risk
5) FPGA adopts high-speed CMOS technology with low power consumption and can be compatible with CMOS and TTL levels< It can be said that FPGA chip is one of the best choices for small batch system to improve system integration and reliability.
7. This thing is simple: first find an 8-way analog switch, that is, choose which of the front-end 8-way analog switches to enter the ad chip through the power of 2.. Then according to your acquisition conversion requirements, select AD converter, a few bit solution, how much conversion rate, this is your own thing. Of course, ad can choose serial and parallel. Finally, to the ad control part, randomly lead out the FPGA pin to connect to the ad chip, the control program and data transmission is also your own business
the choice of chips depends on your requirements. It is absolutely necessary to choose a chip that is high enough.
the choice of chips depends on your requirements. It is absolutely necessary to choose a chip that is high enough.
8. Brother Dei, have you finished? Can you share it
9. If you use Actel's fuion series chips, you don't need to buy ad conversion, it has been integrated into FPGA
if the data is only collected, the data sent by ad is sampled many times, averaged and stored in RAM.
if the data is only collected, the data sent by ad is sampled many times, averaged and stored in RAM.
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