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1. 1. Design input

1) design behavior or structure description

2) the typical text input tools are UltraEdit-32 and editplus.exe

3) typical graphical input tool - mentor's Renoir

4) I think UltraEdit-32 is the best

2. Code debugging

1) do code debugging and syntax checking for the design input file< 2) Debussy is a typical tool

3. Pre simulation

1) functional simulation

2) verification logic model (without time delay)

3) typical tools are Modelsim of mentor, VCs and VSS of Synopsys, active of aldec and NC of cadense

4) in my opinion, the VCs and VSS of Synopsys company are the fastest, and the debugger is the best. Modelsim of mentor company is the fastest for reading and writing files, and the waveform window is easy to use

4. Synthesis

1) translate the design into the original target process

2) optimization

3) suitable area and performance requirements

4) typical tools include leonardospectrum from mentor, DC from Synopsys and Synplify from Synplicity

5) it is recommended for beginners to use leonardospectrum of mentor company. Because it has the best speed and area after simple constraint synthesis, if you know more about the synthesis tool, you can use Synplify of Synplicity company<

5. Layout and wiring

1) mapping design to the specified position in the target process

2) the specified wiring resources should be used

3) as there are only Altera, Xilinx, lattice, Actel, QuickLogic and ATMEL in the PLD market, the first five of them are professional PLD companies, and the first three occupy almost 90% of the market share, We generally use Altera, Xilinx's PLD, so the typical layout and wiring tools are Altera's Quartus II and maxplus II, Xilinx's ise and foudation

4) maxplus II and foudation are the first generation procts of Altera company and Xilinx company respectively, so Quartus II and ISE are generally used for layout and wiring

6. Post simulation

1) timing simulation

2) verification design can work in the target process (using time delay) once programmed or configured

3) the tools used are the same as the software used in the previous simulation

7. Timing analysis

1) generally use the timing analysis tool of layout and wiring tools, or use primetime software of Synopsys company and tau timing analysis software of mentor graphics company

8. Verify that it meets the performance specification

1) verify that it meets the performance specification. If not, go back to the first step

9. Layout design

1) verify the layout design

2) on board programming and device testing

2. The FPGA you buy is based on SRAM technology. The power down program will disappear, but the program will exist in SRAM at run time. JTAG is generally used for debugging. When it is powered on, the program is burned into SRAM, and the power is off; As is an active mode. FGPA actively reads data from EPCs chip and puts it into SRAM when it is powered on. In this way, it can also work. At the moment of power on, FPAG will read data from EPCs and then work normally, so it's like burning it into FPGA. PS is a passive mode, which is used by an external CPU to input program to FPGA. Therefore, if you want to "burn the program to the inside", you should burn the program to EPCs in as mode. Every time you power on, FPGA will read data from it and then run normally. It looks like it's burned in the FPGA. If you want to "really" burn into the FPGA, there is a FPGA based on flash technology, which can be directly burned into the flash in the FPGA, so you don't need ECPs chip, but it's not commonly used in commercial or civil fields
the board you bought is not like this
on chip memory means that FPGA uses internal resources to form a ram or ROM. FPGA is full of ram, this is no problem. The ROM is actually a ram, but when it is powered on, the FPGA reads the fixed information from the EPCs and puts it into the ram, so it is just like a ROM.

3. Learning steps:

1, computer is essential. You can choose to install Quartus II or ISE software. This is the necessary software environment
2. Familiar with Verilog language or VHDL language, familiar with QuartusII or ISE software
3. Design a small code and download it to the target board to see the results
4. Design slightly complex code and download it to the target board to see the results
5. Design complex code and download it to the target board to see the results
6. Design high-speed interface, such as DDR2 or high-speed serial interface
7. Design a complex protocol, such as USB, pciexpress, image codec, etc
8. Learn and learn again, knowing that "there is no end to learning, there is a mountain outside the mountain"
precautions: the first step: learn to understand the structure of FPGA, what FPGA is and what is in the chip. Don't take a development board to program according to other people's things at the beginning
Step 2: master the process of FPGA design. Understand what each step is doing and why
Step 3: start learning the code. Don't go astray in the beginning
Step 4: template is very important. Whether we can make efficient use of FPGA resources, one is to understand the FPGA structure, the other is to understand the logic function and basic mechanism to be realized, and the third is to use the correct template
summary: understanding timing and logic is a matter of time. When you don't think clearly in the early stage of design, you can draw a timing diagram, which will make the idea clearer. In addition, simulation is very important. Don't load the program into FPGA after writing it. First of all, simulate it, especially for larger programs. Imagine that you are doing ASIC, There is no second chance, so the simulation must be done well.

4. This is not very difficult. You can find it on the Internet, and then modify it according to your needs. Format: Subtotal (funct)