How to get to Quanzhou Strait Sports Center in Putian
Publish: 2021-05-17 08:21:09
1. Select the model with GTP for FPGA. Go to the official website of xinlinx to find the demo circuit of this series of FPGA. There are detailed documents, schematic diagrams and PCB. They are all source files. You can use them if you change them directly!
2. Download the Bigfoot plug-in, which is available on it
3. 1) Xilinx FPGA has Aerospace level, Altera does not, so there is no Altera share in aerospace military procts, while Xilinx has
2) compared with Altera, Xilinx is always a little higher in speed and other performance
3) in terms of FPGA resources, Xilinx has more short-term resources than Altera, that is to say, Xilinx is easier to deploy when logic resources are full
at the same time, e to the design of more short-term resources, the cost of Xilinx devices with the same speed level and logic resources is higher than Altera's, which is reflected in the final price. Therefore, as long as Altera's can meet your design, it will have higher cost performance than Xilinx
4) in terms of software, the ease of use of the integrated interface of quartus is better than that of ise, and the script support of ISE is better than that of quartus; Therefore, for beginners, quartus is easier to get started, while for skilled users, ISE is more convenient in the development of large-scale design projects, because it can control and automate the back-end design more precisely.
2) compared with Altera, Xilinx is always a little higher in speed and other performance
3) in terms of FPGA resources, Xilinx has more short-term resources than Altera, that is to say, Xilinx is easier to deploy when logic resources are full
at the same time, e to the design of more short-term resources, the cost of Xilinx devices with the same speed level and logic resources is higher than Altera's, which is reflected in the final price. Therefore, as long as Altera's can meet your design, it will have higher cost performance than Xilinx
4) in terms of software, the ease of use of the integrated interface of quartus is better than that of ise, and the script support of ISE is better than that of quartus; Therefore, for beginners, quartus is easier to get started, while for skilled users, ISE is more convenient in the development of large-scale design projects, because it can control and automate the back-end design more precisely.
4. It's more appropriate to check the configuration of this model by yourself.
5. 1. Post fast, I'm not sure about this problem
2. Translate: to convert VHDL or Verilog into device metalanguage, and select different devices, the conversion results will be different
map: layout, and place the converted components in FPGA according to certain rules, and the principle is to disperse as much as possible, The area constraint can be used to control
route: routing. According to the result of map, the optimal connection within FPGA is calculated. The effort level is set differently, and the result is generally different.
behavioral is generally called behavior simulation or function simulation, also called pre simulation, and the other three are called post simulation. This simulation only tests the function, It does not contain any gate circuit and line delay information, that is to say, functional simulation only represents functional correctness, but if the code writing is unreasonable, there may be timing problems caused by wiring
by the way, behavioral simulation only needs to pass the synthesis size of the code, There is no need for other steps
post translate refers to the simulation after code synthesis and translation. This simulation mainly adds the delay information of gate circuit, and does not calculate the delay of wiring
post translate simulation needs to be executed after translation to execute
post map, as above, the simulation can be executed after synthesis, translation and map of engineering, This simulation will calculate the gate circuit delay and path delay, but it should be noted that since there is no route, the path delay here is calculated theoretically, and generally the actual wiring delay will be greater
post route, that is, after synthesizing, translating, map and route the project, all the real delay information will be calculated, Then simulate
3. Have is the pre simulation, also known as the power simulation, and the others are the post simulation
4. The time sequence constraint is mainly used to control the comprehensive results of the project. If you do not add the time sequence constraint, ISE will automatically add one as the basis for execution. Maybe the result without synthesis can pass, but if you want to be reliable, it's better to add it, so that the report is more reliable
2. Translate: to convert VHDL or Verilog into device metalanguage, and select different devices, the conversion results will be different
map: layout, and place the converted components in FPGA according to certain rules, and the principle is to disperse as much as possible, The area constraint can be used to control
route: routing. According to the result of map, the optimal connection within FPGA is calculated. The effort level is set differently, and the result is generally different.
behavioral is generally called behavior simulation or function simulation, also called pre simulation, and the other three are called post simulation. This simulation only tests the function, It does not contain any gate circuit and line delay information, that is to say, functional simulation only represents functional correctness, but if the code writing is unreasonable, there may be timing problems caused by wiring
by the way, behavioral simulation only needs to pass the synthesis size of the code, There is no need for other steps
post translate refers to the simulation after code synthesis and translation. This simulation mainly adds the delay information of gate circuit, and does not calculate the delay of wiring
post translate simulation needs to be executed after translation to execute
post map, as above, the simulation can be executed after synthesis, translation and map of engineering, This simulation will calculate the gate circuit delay and path delay, but it should be noted that since there is no route, the path delay here is calculated theoretically, and generally the actual wiring delay will be greater
post route, that is, after synthesizing, translating, map and route the project, all the real delay information will be calculated, Then simulate
3. Have is the pre simulation, also known as the power simulation, and the others are the post simulation
4. The time sequence constraint is mainly used to control the comprehensive results of the project. If you do not add the time sequence constraint, ISE will automatically add one as the basis for execution. Maybe the result without synthesis can pass, but if you want to be reliable, it's better to add it, so that the report is more reliable
6. It depends on the internal resources of FPGA, and the few resources are not expensive. It's just that it's not enough to do big projects, but it's OK to buy and play.
7.
The differences between rx5808g and rx580oc and rx5802048p are: different core frequency, different video frequency and different power interface
The core frequency of rx580 8g is 1340mhz The core frequency of rx580oc is 1370mhz The core frequency of rx580 2048p is 1294mhz The frequency of rx580 8g: rx580 8g is 8000MHz The frequency of rx580oc is 8000MHz The frequency of rx580 2048p is 7000mhz The power interface of rx580 8g: rx580 8g is 8pin The power interface of rx580oc is 6pin The power interface of rx580 2048p is 8pin8. I feel it's between 1060 and 1070. I think 1060 is better for cost performance
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